3.4.3.6.4 Implications of Variable NVM Wait States

The NVM Wait states are currently fixed at three, supporting a 4-cycle NVM read access time, and the nature of the PBU/NVM data access handshake is not sensitive to NVM access time. However, variable access times could be advantageous:

  1. Devices are designed to target maximum frequency, and the NVM read access time is based upon this requirement. But not all applications will require full-speed operation and/or may be willing to trade-off speed for lower power consumption. Consequently, it may be desirable to allow the user to select fewer (or no) NVM read access Wait state when operating at lower frequencies. This will improve the IC/ISB miss latency and decrease the effective CPI (clocks per instruction) metric, improving overall device execution efficacy.
  2. Slower Flash panels will consume less power so future devices may support different speed NVM. Zero Wait state linear code execution directly from Flash would, of course, no longer be possible but would rely on the ISB and IC implementations.