12.4.7.1 Clock Monitor Overview

The clock monitor is primarily used for constant clock monitoring in real time with the following added features:

  • Monitored Clock Frequency Drift Detection
  • Under/Over Clocking Warning Detection
  • Under/Over Clocking Failing Detection
  • Monitored Clock Catastrophic Detection
  • Reference Clock Detection
  • Unable to Start
  • Failure After Normal Start

Clock monitoring operates on two different clock sources to accomplish its task, both of which are user selectable from various different clock inputs. Refer to WINSEL and CNTSEL within CMxSEL.

WINSEL selects a reference clock, and CNTSEL selects a monitored clock. The reference clock is used to generate a user-programmable time window defining a known accumulation time period, specified by WINPR[31:0] bits in the CMxWINPR register, over which the monitored clock is allowed to advance the internal counter, thus accumulating its count value.

As each accumulation time period ends, the monitored clock count value is captured into a separate Data Buffer register, see BUF[31:0] in register CMxBUF, while the new accumulation time period begins with a cleared accumulator.

Simultaneously, the ClkxReadyInterrupt is invoked to notify software of the new BUF[31:0] capture contents. The buffer contents are then evaluated by a digital comparator, where various detections are made based on the set and user-defined criteria. Four independent threshold limit registers are employed to allow the user to define the acceptable ranges of the monitored clock frequency. The process is repeated until the module is disabled.

Figure 12-14. Monitor Function

Based on the user selected timings on the reference clock, the start and stop points are chosen to define the desirable time window to accumulate the count value of the counter. The start time initializes the counter to zero and begins adding monitored clock rising edges to itself, whereas the stop time initiates transfer of the accumulated count into the BUF[31:0] register for use by the comparators and software.

Note:
  1. Longer time windows provide more available time for the counter to accumulate monitored clocks, resulting in higher precision.
  2. Choosing the source of the reference clock wisely can significantly improve the performance of the module. If monitored clock frequency is significantly higher than that of the reference clock or frequencies are close to each other, then performance may be affected.
Figure 12-15. Internal Timing Diagram – WINPR[31:0] = 1
Note: Synchronization is intended for illustration only and may not be drawn to scale.
Note:

Upon successful count value capturing into the Data Buffer register:

  • Count ready interrupt output based on the capturing of the counter invoked
  • BUFV set high