32.3.1.2.1 Sleep Mode Entry

  1. The Primary Oscillator (POSC) and Auxuliary Oscillator are disabled.
  2. The Secondary Oscillator (SOSC) continues to run if the Secondary Oscillator Enable bit (SOSC_EN) in the Oscillator Control register (OSCCTRL[3]) is set. For details, refer to the “Oscillator Module” section of the data sheet.
  3. The WDT, clock source and LPRC Oscillator continue to run if the Watchdog Timer is enabled. The WDT, if enabled, is automatically cleared prior to entering Sleep mode. For details, see the “Watchdog Timer” section of the data sheet.
  4. Any attempt to wake up the device while going into Sleep results in erratic behavior.
  5. If any peripheral requests the FRC clock in Sleep mode, then FRC will remain active. Also, the FRC Oscillator can be operated in Low-Power mode. This is controlled by the FRCLPWR[1:0] bits in the Oscillator Configuration register (OSCCFG[17:16]). For details, refer to the “Oscillator Module” section.
  6. The peripherals operating with the system clock are disabled. Optionally, the peripherals can operate in Sleep mode using specific clock sources.
  7. The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode because the system clock is disabled.
To minimize current consumption in Sleep mode, do the following:
  • Ensure that I/O pins do not drive resistive loads
  • Ensure that I/O pins configured as inputs are not floating
  • Disable the SOSC
  • Disable the WDT