12.10.11 PIR2

Peripheral Interrupt Request Register 2

Note: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.

Name:	PIR2
Offset:	0x008E


Bit	7	6	5	4	3	2	1	0
		CCP2IF	CCP1IF		TMR4IF	TMR2IF	TMR3GIF	TMR3IF
Access		R/W/HS	R/W/HS		R/W/HS	R/W/HS	R/W/HS	R/W/HS
Reset		0	0		0	0	0	0

Bit 6 – CCP2IF CCP2 Interrupt Flag


Value	CCP Mode
Value	Capture	Compare	PWM
`1`	Capture occurred (must be cleared in software)	Compare match occurred (must be cleared in software)	Output trailing edge occurred (must be cleared in software)
`0`	Capture did not occur	Compare match did not occur	Output trailing edge did not occur

Bit 5 – CCP1IF CCP1 Interrupt Flag


Value	CCP Mode
Value	Capture	Compare	PWM
`1`	Capture occurred (must be cleared in software)	Compare match occurred (must be cleared in software)	Output trailing edge occurred (must be cleared in software)
`0`	Capture did not occur	Compare match did not occur	Output trailing edge did not occur

Bit 3 – TMR4IF TMR4 Interrupt Flag

Value	Description
1	TMR4 interrupt has occurred (must be cleared in software)
0	TMR4 interrupt event has not occurred

Bit 2 – TMR2IF TMR2 Interrupt Flag

Value	Description
1	TMR2 interrupt has occurred (must be cleared in software)
0	TMR2 interrupt event has not occurred

Bit 1 – TMR3GIF TMR3 Gate Interrupt Flag

Value	Description
1	The TMR3 Gate has gone inactive (must be cleared in software)
0	TMR3 Gate is active

Bit 0 – TMR3IF TMR3 Interrupt Flag

Value	Description
1	TMR3 interrupt has occurred (must be cleared in software)
0	TMR3 interrupt event has not occurred

Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.