12.10.10 PIR1
Note: Interrupt flag bits are set when an
Interrupt condition occurs, regardless of the state of its corresponding enable bit or
the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag
bits are cleared before enabling an interrupt.
Name: | PIR1 |
Offset: | 0x008D |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TMR1GIF | TMR1IF | OSFIF | CSWIF | ACTIF | SCANIF | CRCIF | NVMIF | ||
Access | R/W/HS | R/W/HS | R | R | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – TMR1GIF TMR1 Gate Interrupt Flag
Value | Description |
---|---|
1 | The TMR1 Gate has gone inactive (must be cleared in software) |
0 | TMR1 Gate is active |
Bit 6 – TMR1IF TMR1 Interrupt Flag
Value | Description |
---|---|
1 | TMR1 interrupt has occurred (must be cleared in software) |
0 | TMR1 interrupt event has not occurred |
Bit 5 – OSFIF Oscillator Failure Interrupt Flag
Value | Description |
---|---|
1 | An oscillator failure event has been detected (must be cleared in software) |
0 | An oscillator failure event has not been detected |
Bit 4 – CSWIF Clock Switch Interrupt Flag
Value | Description |
---|---|
1 | A Clock Switch interrupt has occurred (must be cleared in software) |
0 | A Clock Switch interrupt event has not occurred |
Bit 3 – ACTIF Active Clock Tuning Interrupt Flag
Value | Description |
---|---|
1 | Active Clock Tuning interrupt occurred (must be cleared in software) |
0 | Active Clock Tuning interrupt event has not occurred |
Bit 2 – SCANIF Memory Scanner Interrupt Flag
Value | Description |
---|---|
1 | Memory Scanner interrupt has occurred (must be cleared in software) |
0 | Memory Scanner interrupt event has not occurred |
Bit 1 – CRCIF CRC Interrupt Flag
Value | Description |
---|---|
1 | CRC interrupt has occurred (must be cleared in software) |
0 | CRC interrupt event has not occurred |
Bit 0 – NVMIF Nonvolatile Memory (NVM) Interrupt Flag
Value | Description |
---|---|
1 | The requested NVM operation has completed (must be cleared in software) |
0 | NVM interrupt event has not occurred |