38.8.11 Timeout Counter Configuration

This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
Name: TOCC
Offset: 0x28
Reset: 0xFFFF0000
Property: Write-restricted

Bit 3130292827262524 
 TOP[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 2322212019181716 
 TOP[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      TOS[1:0]ETOC 
Access R/WR/WR/W 
Reset 000 

Bits 31:16 – TOP[15:0] Timeout Period

Start value of the Timeout Counter (down-counter). Configures the Timeout Period.

Bits 2:1 – TOS[1:0] Timeout Select

When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored.
ValueNameDescription
0x0 CONT Continuous operation.
0x1 TXEF Timeout controlled by TX Event FIFO.
0x2 RXF0 Timeout controlled by Rx FIFO 0.
0x3 RXF1 Timeout controlled by Rx FIFO 1.

Bit 0 – ETOC Enable Timeout Counter

ValueDescription
0 Timeout Counter disabled.
1 Timeout Counter enabled.