27.6.7 Status


Bit	15	14	13	12	11	10	9	8
			BPHL	DBPE	BOOTPROT[3:0]
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	x


Bit	7	6	5	4	3	2	1	0
			BPDIS	AFIRST	SUSP	LOAD	PRM	READY
Access			R	R	R	R	R	R
Reset			0	1	0	0	0	0

Bit 13 – BPHL Boot Protect Hard Lock

This bit is loaded 1 when the BPHL fuse is programmed (SBPHL command is executed successfully).

Bit 12 – DBPE Dual Boot Protection Enable

If the BPHL fuse is programmed, the bit is loaded with the DBPE value programmed during the BPHL protection sequence.

If the BPHL fuse is erased, this bit is always read zero.

When set, BOOTSIZE from each BANK A and BANK B are protected against modification (write, erase).

When erased, BOOTSIZE from 0x0000_0000 is protected against modifications (write or erase).

When the security bit is cleared, the DBPE bit is read zero.

Bits 11:8 – BOOTPROT[3:0] Boot Loader Protection Size

Defines the size of the BOOTPROT region which is protected against write or erase or Chip-Erase operations. This size is given by the following formula (15-BOOTPROT)*8KB.

When the BPHL bit is cleared, this bitfield is loaded from fuse bits located in the User row (UROW), during the device startup.

When the BPHL bit is set, this bitfield is loaded from the BOOTPROT programmed value during the BPHL protection sequence, and reflects the BOOTPROT value from the User Row, when the Set Boot Protect Hard Lock command was issued.

Bit 5 – BPDIS Boot Loader Protection Disable

0: Boot loader protection is not discarded.

1: Boot loader protection against modify operations is discarded until CBPDIS is issued or next start-up sequence except for Chip-Erase.

Note: If the STATUS.BPHL=1, the BPDIS setting is ignored and the boot loader protection is always enabled.

Bit 4 – AFIRST BANKA First

0: Start address of bank B is mapped at 0x0000_0000.

1: Start address of bank A is mapped at 0x0000_0000.

Bit 3 – SUSP NVM Write Or Erase Operation Is Suspended

0: The NVM controller is not in suspended state.

1: The NVM controller is in suspended state.

Bit 2 – LOAD NVM Page Buffer Active Loading

This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load has been performed, this flag is set, and it remains set until a Write Page (WP), Write Quad Word (WQW) or a page buffer clear (PBCLR) command is given.

Bit 1 – PRM Power Reduction Mode

This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two ways: through the command interface or automatically when entering sleep with CTRLA.PRM set accordingly. PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM and CPRM) or when exiting sleep with CTRLA.PRM set accordingly.

0: NVM is not in power reduction mode

1: NVM is in power reduction mode.