The output compare register
contains a 16-bit value that is continuously compared with the counter value (T5CNT).
The T5OCRL represents the lower byte of the compare value. To ensure that both the high
and low bytes are written simultaneously when the CPU writes to these registers, the
access is performed using an 8-bit temporary high-byte register (TEMP). This temporary
register is shared by all the other 16-bit registers.
See Accessing 16-bit
Registers in the Timer5 from Related Links.
Name:
T5OCRL
Offset:
0x08A
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
T5OCR[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – T5OCR[7:0] Timer5 Compare Counter Value Low Byte
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
