4.9.7.6.1.6 T5CNTH – Timer5 Counter Register High Byte
The T5CNTH/L registers provide
direct access, both for read and for write operations to the 16-bit counter. The T5CNTH
register represents the upper byte of the counter value. To ensure that both the high
and low bytes are read and written simultaneously when the CPU accesses these registers,
the access is performed using an 8-bit temporary high-byte register (TEMP). This
temporary register is shared by all the other 16-bit registers.
See Accessing
16-bit Registers in the Timer5 from Related Links. Modifying T5CNTH
while the counter is running processes poses the risk of missing a compare match
between T5CNT and the T5OCR register. Writing to the T5CNTH register blocks
(removes) the compare match on the following timer clock.
Name:
T5CNTH
Offset:
0x08E
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
T5CNT [15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – T5CNT [15:8] Timer5 Counter Value High Byte
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
