4.9.7.6.1.3 T5IMR – Timer5 Interrupt Mask Register
| Name: | T5IMR |
| Offset: | 0x08F |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | T5CIM | T5OIM | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 1 – T5CIM Timer5 Output Compare Match Interrupt Enable
If this bit is written to
‘1’ and the I flag in SREG is set (interrupts globally
enabled), the Timer5 output compare match interrupt is enabled. The corresponding
interrupt vector is executed when the T5IFR.T5COF flag is set. See Reset and
Interrupt Handling from Related Links.
Bit 0 – T5OIM Timer5 Overflow Interrupt Enable
If this bit is written to
‘1’ and the I flag in SREG is set (interrupts globally
enabled), the Timer5 overflow interrupt is enabled. The corresponding interrupt
vector is executed when the T5IFR.T5OFF flag is set. See Reset and Interrupt
Handling from Related Links.
