1.1.3 High-Speed Memory Interfaces

The following list provides the characteristics of the high-speed memory interfaces:

  • Up to two high-speed DDRx memory controllers
    • High-Performance Memory Subsystem (HPMS) Double Data Rate (DDR) (DDR2/3 controller in HPMS (MDDR)) and fabric DDR (DDR2/3 Controller in FPGA Fabric (FDDR)) controllers
    • Supports LPDDR/DDR2/DDR3
    • Maximum 333 MHz clock rate
    • Single Error Correct Double Error Detect (SECDED) enable/disable feature
    • Supports various DRAM bus width modes, ×8, ×9, ×16, ×18, ×32, and ×36
    • Supports command reordering to optimize memory efficiency
    • Supports data reordering, returning critical word first for each command
  • SDRAM support through a soft SDRAM memory controller.