13.5.1 PMD0
Note:
- When enabling NVM, a delay of up to 1 μs may be required before accessing data.
| Name: | PMD0 |
| Offset: | 0x796 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SYSCMD | FVRMD | NVMMD | CLKRMD | IOCMD | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SYSCMD Disable Peripheral System Clock Network bit
Disables the System clock network
| Value | Description |
|---|---|
1 |
System clock network disabled (FOSC) |
0 |
System clock network enabled |
Bit 6 – FVRMD Disable Fixed Voltage Reference bit
| Value | Description |
|---|---|
1 |
FVR module disabled |
0 |
FVR module enabled |
Bit 2 – NVMMD NVM Module Disable bit(1)
Disables the NVM module
| Value | Description |
|---|---|
1 |
All Memory reading and writing is disabled; NVMCON registers cannot be written; FSR access to these locations returns zero. |
0 |
NVM module enabled |
Bit 1 – CLKRMD Disable Clock Reference bit
| Value | Description |
|---|---|
1 |
CLKR module disabled |
0 |
CLKR module enabled |
Bit 0 – IOCMD Disable Interrupt-on-Change bit, All Ports
| Value | Description |
|---|---|
1 |
IOC module(s) disabled |
0 |
IOC module(s) enabled |