18.7.9 DFLL48M Control B

Note: In the period of 80-100 us between lock and stabilization, DFLL accuracy will be limited to +/-1.5%. After stabilization has been achieved, the accuracy will be +/-0.25%. Disabling Quick Lock will eliminate this period of inaccuracy.
Table 18-12. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: DFLLCTRLB
Offset: 0x30
Reset: 0x00000000
Property: PAC Write-Protected, Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 WAITLOCK QLDISCCDIS LLAWSTABLELOOPEN 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 7 – WAITLOCK Wait Lock

This bit controls the DFLL48M output clock, depending on lock status:

ValueDescription
0 Output clock before the DFLL is locked.
1 Output clock when DFLL is locked.

Bit 5 – QLDIS Quick Lock Disable

ValueDescription
0 Quick Lock is enabled.
1 Quick Lock is disabled.

Bit 4 – CCDIS Chill Cycle Disable

ValueDescription
0 Chill Cycle is enabled.
1 Chill Cycle is disabled.

Bit 2 – LLAW Lose Lock After Wake

ValueDescription
0 Locks will not be lost after waking up from sleep modes if the DFLL clock has been stopped.
1 Locks will be lost after waking up from sleep modes if the DFLL clock has been stopped.

Bit 1 – STABLE Stable DFLL48M Frequency

ValueDescription
0 Tune register tracks changes in output frequency.
1 Tune calibration register value will be fixed after a lock.

Bit 0 – LOOPEN Operating Mode Selection

ValueDescription
0 The DFLL operates in open-loop operation.
1 The DFLL operates in closed-loop operation.