18.7.13 PLL0 Control

Table 18-16. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PLL0CTRL
Offset:	0x40
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
			BWSEL[2:0]			REFSEL[2:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ONDEMAND					WRTLOCK	ENABLE
Access	R/W					R/W	R/W
Reset	0					0	0

Bits 13:11 – BWSEL[2:0] Bandwidth Selection

These bits select the PLL closed loop filter bandwidth, depending on the frequency after the reference divider F_PFD as shown in the table below. Selecting the correct filter bandwidth is important to operate the PLL'VCO in its best range.

Table 18-17. PLL0 BWSEL Filter
F_PFD	BWSEL[2:0]
Reserved	0b000
4MHz ≤ F_PFD < 10MHz	0b001
10MHz ≤ F_PFD < 20MHz	0b010
20MHz ≤ F_PFD < 30MHz	0b011
30MHz ≤ F_PFD < 60MHz	0b100
Reserved	0b101 – 0b111

Note:

F_PFD is the frequency of the reference clock divided by the PLL0 reference divider PLLREFDIV.REFDIV. These bits are PLLCTRL0.ENABLE protected and cannot be updated if PLLCTRL0.ENABLE =1.
At elevated temperatures, the effective range of the Bandwidth setting will skew higher. Depending on the input frequency and operating temperature, it may be optimal to change the BWSEL setting to the next higher value.

Bits 10:8 – REFSEL[2:0] Reference Selection

These bits select the PLL0 clock reference, as shown in the table below.


REFSEL[2:0]	Selectedsource	Description
0x0 ^(2,3)	GCLK	DedicatedGCLK_PLL0_REF clock reference
0x1	XOSC	XOSC clock reference
0x2	DFLL48M	DFLL48Mclock reference
0x3- 0x7	n/a	Reserved

Important: If GCLK source is PLL0, then users should not use GCLK_PLL0_REF as input clock source to PLL0. It will create a circular reference, an unstable clock, and unexpected behavior.

Note:

These bits are PLLCTRL0.ENABLE protected and cannot be updated if PLLCTRL0.ENABLE = 1.
The recommended clock sources for PLL0 are XOSC and DFLL48M. Using the GLCK as a source is not recommended.

Bit 7 – ONDEMAND On Demand Control

The ONDEMAND operation mode allows the PLL to be enabled or disabled depending on peripheral clock requests.

Note: If ONDEMAND is set, the PLL will only be running when requested by a peripheral and enabled (PLLCTRL. ENABLE = 1). If there is no peripheral requesting the PLL’s clock source, the PLL will be in a disabled state. If ONDEMAND is disabled the PLL will always be running when enabled (PLLCTRL.ENABLE = 1). In Standby Sleep mode, the ONDEMAND operation is still active.

This bit is PLLCTRL0.ENABLE protected and cannot be updated if PLLCTRL0.ENABLE =1.

Value	Description
0	The PLL0 is always on.
1	The PLL0 is running when a peripheral is requesting the PLL to be used as a clock source. The PLL is not running if no peripheral is requesting the PLL clock source.

Bit 2 – WRTLOCK Write Lock

Note: Once the WRTLOCK bit is set, it can only be cleared by a reset.

Value	Description
0	The PLLCTRL, PLLFBDIV, PLLREFDIV and PLLPOSTDIVA/B registers can be modified by a system write.
1	The PLLCTRL, PLLFBDIV, PLLREFDIV and PLLPOSTDIVA/B registers are write protected, except for bits PLLPOSTDIVA.OUTENn.

Bit 1 – ENABLE PLL0 Enable

Value	Description
0	The PLL0 oscillator is disabled.
1	The PLL0 oscillator is enabled.