18.7.17 PLL0 Post Output Clock Divider B
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PLL0POSTDIVB |
| Offset: | 0x50 |
| Reset: | 0x00002020 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OUTEN5 | POSTDIV5[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OUTEN4 | POSTDIV4[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 7, 15 – OUTENn CLK_PLL0_CLKOUTn Output Enable
| Value | Description |
|---|---|
| 0 | CLK_PLL0_CLKOUTn Output Disabled |
| 1 | CLK_PLL0_CLKOUTn Output Enabled |
Bits 0:5, 8:13 – POSTDIVn PLL0 FVCO Output Clock Division Factor
This field determines the division factor of the PLL0 FVCO output that
creates FCLK_PLL0 and CLK_PLL0_CLKOUTn. POSTDIV value must be between 1 ≤
POSTDIV ≤ 63.
Note:
- (FVCO/POSTDIV) > FCLK_PLL0 > CLK_PLL0_CLKOUTn.
- PLL0 must be disabled before making changes to POSTDIVn values.
- It is not recommended to set the POSTDIV registers while the PLL is active and stable.