18.7.8 DFLL48M Control A
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DFLLCTRLA |
| Offset: | 0x2C |
| Reset: | 0x00000082 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ONDEMAND | LOWFREQ | WRTLOCK | ENABLE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 0 | 0 | 1 |
Bit 7 – ONDEMAND On Demand Control
The ONDEMAND operation mode allows the DFLL to be enabled or disabled depending on peripheral clock requests.
Note: If ONDEMAND is set, the DFLL will only be running when requested by a
peripheral and enabled (DFLLTRLA. ENABLE=1). If there is no peripheral
requesting the DFLL’s clock source, the DFLL will be in a disabled state. If
ONDEMAND is disabled the DFLL will always be running when enabled
(DFLLTRLA.ENABLE=1). In standby sleep mode, the ONDEMAND operation is still
active This bit is DFLLCTRLA.ENABLE protected and cannot be updated if
DFLLCTRLA.ENABLE=1.
| Value | Description |
|---|---|
| 0 | The DFLL is always on. |
| 1 | The DFLL is running when a peripheral is requesting the DFLL to be used as a clock source. The DFLL is not running if no peripheral is requesting the clock source. |
Bit 3 – LOWFREQ Low Frequency Mode
Note: This bit is DFLLCTRLA.ENABLE protected and cannot be updated if
DFLLCTRLA.ENABLE=1.
| Value | Description |
|---|---|
| 0 | The DFLL48M oscillator operates at high frequency. |
| 1 | The DFLL48M oscillator operates at low frequency. |
Bit 2 – WRTLOCK Write lock
Note: Once the WRTLOCK bit is set, it can only be cleared by a reset.
| Value | Description |
|---|---|
| 0 | The DFLLCTRLA and DFLLCTRLB registers can be modified by a system write. |
| 1 | The DFLLCTRLA and DFLLCTRLB registers are write protected. |
Bit 1 – ENABLE DFLL48M Enable
Note: This bit is write-synchronized:
Due to synchronization, there is delay from updating the register until the
peripheral is enabled/disabled. The value written to DFLLCTRLA.ENABLE will read
back immediately after written.
| Value | Description |
|---|---|
| 0 | The DFLL48M oscillator is disabled. |
| 1 | The DFLL48M oscillator is enabled. |