18.7.16 PLL0 Post Output Clock Divider A

Important: The PLL0 frequency cannot be changed on the fly while it's the active enabled clock to the system.

PLL0 Output Clocks:

CLK_PLL0_CLKOUTn where n = 0.
CLK_PLL0_CLKOUTn where n = 1.
CLK_PLL0_CLKOUTn where n = 2.
CLK_PLL0_CLKOUTn where n = 3.

Table 18-20. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PLL0POSTDIVA
Offset:	0x4C
Reset:	0x20202020
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	OUTEN3		POSTDIV3[5:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		1	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	OUTEN2		POSTDIV2[5:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		1	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	OUTEN1		POSTDIV1[5:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		1	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	OUTEN0		POSTDIV0[5:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		1	0	0	0	0	0

Bits 7, 15, 23, 31 – OUTENn CLK_PLL0_CLKOUTn Output Enable

Value	Description
0	CLK_PLL0_CLKOUTn Output Disabled
1	CLK_PLL0_CLKOUTn Output Enabled

Bits 0:5, 8:13, 16:21, 24:29 – POSTDIVn PLL0 FVCO Output Clock Division Factor

This field determines the division factor of the PLL0 F_VCO output that creates FCLK_PLL0 and CLK_PLL0_CLKOUTn. The POSTDIV value must be between 1 ≤ POSTDIV ≤ 63.

Note:

(F_VCO / POSTDIV) > FCLK_PLL0 > CLK_PLL0_CLKOUTn.
PLL0 must be disabled before making changes to POSTDIVn values.
It is not recommended to set the POSTDIV registers while the PLL is active and stable.