30.2.23.10 Flash Write Data Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DATAx |
| Offset: | 0x28 + x*0x04 [x=0..7] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DATA31 | DATA30 | DATA29 | DATA28 | DATA27 | DATA26 | DATA25 | DATA24 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DATA23 | DATA22 | DATA21 | DATA20 | DATA19 | DATA18 | DATA17 | DATA16 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DATA15 | DATA14 | DATA13 | DATA12 | DATA11 | DATA10 | DATA9 | DATA8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA7 | DATA6 | DATA5 | DATA4 | DATA3 | DATA2 | DATA1 | DATA0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DATAx Flash Write Data
The value in this register(s) is written to flash when a Write operation is commanded.
Single Write: (64-bit data)
Writes DATA0 to ADDR[31:3] with address bits [2:0] = 000
Writes DATA1 to ADDR[31:3] with address bits [2:0] = 100
Quad Write: (256-bit data)
Writes DATA0 to ADDR[31:5], with address bits[4:0] = 0_0000
Writes DATA1 to ADDR[31:5], with address bits[4:0] = 0_0100
Writes DATA2 to ADDR[31:5], with address bits[4:0] = 0_1000
Writes DATA3 to ADDR[31:5], with address bits[4:0] = 0_1100
Writes DATA4 to ADDR[31:5], with address bits[4:0] = 1_0000
Writes DATA5 to ADDR[31:5], with address bits[4:0] = 1_0100
Writes DATA6 to ADDR[31:5], with address bits[4:0] = 1_1000
Writes DATA7 to ADDR[31:5], with address bits[4:0] = 1_1100