15.6.6 Peripheral Interrupt Flag Status and Clear B

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGB bit. An interrupt request is generated if INTENCLR/SET.ERR is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the corresponding INTFLAGB interrupt flag.

Table 15-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	INTFLAGB
Offset:	0x18
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
			TCC3	TCC2	TCC1	TCC0	SERCOM3	SERCOM2
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SERCOM1	SERCOM0	EVSYS	IDAU	PRM	DMA1	DMA0	PORT
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

15.6.6 Peripheral Interrupt Flag Status and Clear B

Bits 10, 11, 12, 13 – TCCn Interrupt Flag for Timer Counter Controller, n = 0..3

Bits 6, 7, 8, 9 – SERCOMn Serial Communication Interface n, n = 0..3

Bit 5 – EVSYS Event System

Bit 4 – IDAU Implementation Defined Attribution Unit

Bit 3 – PRM PRM Host Boot ROM

Bits 1, 2 – DMAn Direct Memory Access n = 0..1

Bit 0 – PORT PORT General Purpose Pin I/O Controller