15.6.5 Peripheral Interrupt Flag Status and Clear A

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGA bit. An interrupt request is generated if INTENCLR/SET.ERR is one.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the corresponding INTFLAGA interrupt flag.

Table 15-6. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	INTFLAGA
Offset:	0x14
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	TRAM	PAC	EIC	RTC	WDT	FREQM	MCLK	GCLK
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	OSC32KCTRL	OSCCTRL	RSTC	SUPC	PM	FCW	FCR	DSU
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 15 – TRAM Trust RAM

Bit 14 – PAC Peripheral Access Controller

Bit 13 – EIC External Interrupt Controller

15.6.5 Peripheral Interrupt Flag Status and Clear A

Bit 15 – TRAM Trust RAM

Bit 14 – PAC Peripheral Access Controller

Bit 13 – EIC External Interrupt Controller

Bit 12 – RTC Real Time Clock

Bit 11 – WDT Watchdog Timer

Bit 10 – FREQM Frequency Meter

Bit 9 – MCLK Main Clock

Bit 8 – GCLK Generic Clock Controller

Bit 7 – OSC32KCTRL 32 K Oscillator Controller

Bit 6 – OSCCTRL Oscillator Controller

Bit 5 – RSTC Reset Controller

Bit 4 – SUPC Startup Power Controller

Bit 3 – PM Interrupt Flag for the Power Manager

Bit 2 – FCW Flash Controller Write

Bit 1 – FCR Flash Controller Read

Bit 0 – DSU Device Service Unit