15.6.1 Write Control

Table 15-1. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	WRCTRL
Offset:	0x00
Reset:	0x00000000
Property:	–


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	KEY[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PERID[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PERID[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 23:16 – KEY[7:0] Peripheral Access Control Key

These bits define the peripheral access control key:

Value	Name	Description
0x0	OFF	No action
0x1	CLEAR	Clear the peripheral write control
0x2	SET	Set the peripheral write control
0x3	LOCK	Set and lock the peripheral write control until the next hardware reset

Bits 15:0 – PERID[15:0] Peripheral Identifier

The PERID represents the peripheral whose control is changed using the WRCTRL.KEY.

Table 15-2. PERID Values
Peripheral	PERID	SFR Suffix	Bit	SFR's
Peripheral	PERID	SFR Suffix	Bit	STATUS	INTFLAG
DSU	0	A	0	STATUSA[0]	INTFLAGA[0]
FCR	1	A	1	STATUSA[1]	INTFLAGA[1]
FCW	2	A	1	STATUSA[1]	INTFLAGA[1]
PM	3	A	2	STATUSA[2]	INTFLAGA[2]
SUPC	4	A	3	STATUSA[3]	INTFLAGA[3]
RSTC	5	A	4	STATUSA[4]	INTFLAGA[4]
OSCCTRL	6	A	5	STATUSA[5]	INTFLAGA[5]
OSC32KCTRL	7	A	6	STATUSA[6]	INTFLAGA[6]
GCLK	8	A	7	STATUSA[7]	INTFLAGA[7]
MCLK	9	A	8	STATUSA[8]	INTFLAGA[8]
FREQM	10	A	9	STATUSA[9]	INTFLAGA[9]
WDT	11	A	10	STATUSA[10]	INTFLAGA[10]
RTC	12	A	11	STATUSA[11]	INTFLAGA[11]
EIC	13	A	12	STATUSA[12]	INTFLAGA[12]
PAC	14	A	13	STATUSA[13]	INTFLAGA[13]
TRAM	15	A	14	STATUSA[14]	INTFLAGA[14]
MBISTINTF	18
TDM	19
PORT	20	B	0	STATUSB[0]	INTFLAGB[0]
DMA0	21	B	1	STATUSB[1]	INTFLAGB[1]
DMA1	22	B	2	STATUSB[2]	INTFLAGB[2]
HMATRIX	23	B
CMCC	24	B
PRM	25	B	3	STATUSB[3]	INTFLAGB[3]
IDAU	26	B	4	STATUSB[4]	INTFLAGB[4]
EVSYS	27	B	5	STATUSB[5]	INTFLAGB[5]
SERCOM0	28	B	6	STATUSB[6]	INTFLAGB[6]
SERCOM1	29	B	7	STATUSB[7]	INTFLAGB[7]
SERCOM2	30	B	8	STATUSB[8]	INTFLAGB[8]
SERCOM3	31	B	9	STATUSB[9]	INTFLAGB[9]
TCC0	32	B	10	STATUSB[10]	INTFLAGB[10]
TCC1	33	B	11	STATUSB[11]	INTFLAGB[11]
TCC2	34	B	12	STATUSB[12]	INTFLAGB[12]
TCC3	35	B	13	STATUSB[13]	INTFLAGB[13]
SERCOM4	36	C	0	STATUSC[0]	INTFLAGC[0]
SERCOM5	37	C	1	STATUSC[1]	INTFLAGC[1]
SERCOM6	38	C	2	STATUSC[2]	INTFLAGC[2]
SERCOM7	39	C	3	STATUSC[3]	INTFLAGC[3]
TCC4	40	C	4	STATUSC[4]	INTFLAGC[4]
TCC5	41	C	5	STATUSC[5]	INTFLAGC[5]
TCC6	42	C	6	STATUSC[6]	INTFLAGC[6]
TCC7	43	C	7	STATUSC[7]	INTFLAGC[7]
ADC	44	C	8	STATUSC[8]	INTFLAGC[8]
AC	45	C	9	STATUSC[9]	INTFLAGC[9]
PTC	46	C	10	STATUSC[10]	INTFLAGC[10]
SPI_IXS	47	C	11	STATUSC[11]	INTFLAGC[11]
PCC	48	C	12		INTFLAGC[12]
CCL	49	C	13	STATUSC[13]	INTFLAGC[13]
PDEC	50	C	14	STATUSC[14]	INTFLAGC[14]
CAN0	51
CAN1	52
ETH	53
SQI		D	0	STATUSD[0]	INTFLAGD[0]
TRNG	54	C	15	STATUSC[15]	INTFLAGC[15]
SDMMC0	55
SDMMC1	56
USB	57	C	16	STATUSC[16]	INTFLAGC[16]