46.10.6 Digital to Analog Converter (DAC) Characteristics
| Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| Res | Resolution | - | - | - | 12 | bits |
| clk | Internal DAC Clock frequency | - | - | - | 12 | MHz |
| fs_dac | Sampling frequency | clk/12, CCTRL=0x0 (Low Power) | - | - | 10 | ksps |
| clk/12, CCTRL=0x2 (High Power) | - | - | 1 | Msps | ||
| VOUTmin | Min Output Voltage | - | - | - | 0.15 | V |
| VOUTmax | Max Output Voltage | - | VDDANA-0.15 | - | - | |
| VREF | Reference input | CTRLB.REFSEL[1:0]=0x2 (VREFAB) | 1 | - | VDDANA-0.15 | V |
| CTRLB.REFSEL[1:0]=0x0 (VREFAU) | 1 | - | VDDANA | |||
| CVREF | External decoupling capacitor | - | - | 220 | - | nF |
| CLOAD | Output capacitor load | - | - | - | 50 | pF |
| RLOAD | Output resistance load | - | 5 | - | - | kΩ |
| ts | Settling time | For reaching +/-1LSB of the final value. Step size < 500 LSB - Cload = 50pF | - | - | 1 | µs |
| ts_FS | Settling time 0x080 to 0xF7F | For reaching +/-1LSB of the final value. Step size from 0% to 100% - Cload = 50pF | - | 5 | 7 | µs |
Note:
- These values are based on simulation. They are not covered by production test limits or characterization.
| Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| INL |
Integral Non Linearity, | clk=12MHz, VDDANA=3.0V, External Ref.=2.0V, CLoad=50pF | - | +/-2.5 | +/-3.5 | LSB |
| clk=12MHz, VDDANA=2.0V, internal VDDANA=2.0V, CLoad=50pF | - | +/-2.2 | +/-3.0 | |||
| DNL |
Differential Non Linearity, | clk=12MHz, VDDANA=3.0V, External Ref.=2.0V, CLoad=50pF | - | +/-2.0 | +/-2.5 | LSB |
| clk=12MHz, VDDANA=2.0V, internal VDDANA=2.0V, CLoad=50pF | - | +/-1.5 | +/-2.5 | |||
| Gerr | Gain Error | External Reference voltage | - | +/-0.3 | +/-0.8 | % FSR |
| Internal VDDANA Reference | - | +/-0.2 | +/-0.5 | |||
| 1.0V Internal Reference voltage | - | +/-1 | +/-3.0 | |||
| Offerr | Offset Error | External Reference voltage | - | +/-5.0 | +/-10.0 | mV |
| Internal VDDANA Reference | - | +/-4.0 | +/-10.0 | |||
| 1.0V Internal Reference voltage | - | +/-10.0 | +/-30.0 | |||
| TCg | Gain Drift | -20 | - | 20 | ppm/°C | |
| TCo | Offset Drift | -0.05 | -0.01 | 0.05 | mV/°C | |
| ENOB | Effective Number Of Bits | Fs=1Ms/s - External Ref - High Power | 9.5 | 10.1 | 10.7 | Bits |
| SNR | Signal to Noise ratio | 58.0 | 67.0 | 71.0 | dB | |
| THD | Total Harmonic Distortion | -71.0 | -64.0 | -59.0 | dB |
Note:
- These values are based on characterization.
| Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| INL |
Integral Non Linearity, | clk=12MHz, VDDANA=3.0V, External Ref.=2.0V, CLoad=50pF | - | +/-3 | +/-4.5 | LSB |
| clk=12MHz, VDDANA=2.0V, internal VDDANA=2.0V, CLoad=50pF | - | +/-2.5 | +/-3.5 | |||
| DNL(1) |
Differential Non Linearity, | clk=12MHz, VDDANA=3.0V, External Ref.=2.0V, CLoad=50pF | - | +/-3.0 | +/-4.0 | LSB |
| clk=12MHz, VDDANA=2.0V, internal VDDANA=2.0V, CLoad=50pF | - | +/-2.5 | +/-3.5 | |||
| Gerr | Gain Error | External Reference voltage | - | +/-0.3 | +/-0.8 | % FSR |
| Internal VDDANA Reference | - | +/-0.2 | +/-0.5 | |||
| 1.0V Internal Reference voltage | - | +/-0.1 | +/-3.0 | |||
| Offerr | Offset Error | External Reference voltage | - | +/-5.0 | +/-10.0 | mV |
| Internal VDDANA Reference | - | +/-7.0 | +/-10.0 | |||
| 1.0V Internal Reference voltage | - | +/-10.0 | +/-12.0 | |||
| TCg | Gain Drift | -20 | - | 20 | ppm/°C | |
| TCo | Offset Drift | -0.03 | -0.05 | 0.02 | mV/°C | |
| ENOB | Effective Number Of Bits | Fs=1Ms/s - External Ref - High Power | 9.0 | 10.0 | 10.3 | Bits |
| SNR | Signal to Noise ratio | 56.0 | 67.0 | 68.5 | dB | |
| THD | Total Harmonic Distortion | -69.0 | -65.0 | -55.0 | dB |
Note:
- These values are based on characterization.
| Symbol | Parameters | Conditions | Ta | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|---|
| IDDANA | Differential Mode, DC supply current, 2 output channels - without load | fs=1Msps, CCTRL=0x2, VREF>2.4V, VCC=3.3V | Max.85°C Typ.25°C | - | 401 | 587 | µA |
| fs=10ksps, CCTRL=0x0, VREF<2.4V, VCC=3.3V | - | 84 | 174 | ||||
| IDDANA | Single-Ended Mode, DC supply current, 2 output channels - without load | fs=1Msps, CCTRL=0x2, VREF>2.4V, VCC=3.3V | - | 297 | 395 | µA | |
| fs=10ksps, CCTRL=0x0, VREF<2.4V, VCC=3.3V | - | 53 | 112 |
Note: 1.These values are based on
characterization.
