33.22.28 PMC Asynchronous Partial Wake-Up Enable Register 0
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode register.
| Name: | PMC_SLPWK_ER0 |
| Offset: | 0x0114 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PID30 | PID29 | PID28 | PID27 | PID26 | PID25 | PID24 | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PID23 | PID22 | PID21 | PID20 | PID19 | |||||
| Access | W | W | W | W | W | ||||
| Reset | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 – PIDx Peripheral x Asynchronous Partial Wake-Up Enable
Not all PIDs can be configured with asynchronous partial wake-up.
Only the following PIDs can be configured with asynchronous partial wake-up: FLEXCOMx, SPIx, TWIx, UARTx and ADC.
The clock of the peripheral must be enabled before using its asynchronous partial wake-up function (the associated PIDx field in PMC Peripheral Clock Status register 1 is set to ‘1’).
The values for PIDx are defined in the section “Peripheral Identifiers”.
| Value | Description |
|---|---|
| 0 |
No effect. |
| 1 |
The asynchronous partial wake-up function of the corresponding peripheral is enabled. |