11.4.4.2 IRT Control Register

The IRT control register, IRTCTRL, includes the EAA, DBG, IACT, DONE and PLCK bits. IRTCTRL is read-only except when PLCK bit = ‘0’. The EAA bit controls debug entry when secure debug is enabled. The DBG bit controls debug access to the IRT partition when IRT and debug are enabled. The DBG bit is cleared by a cold Reset (POR or BOR) and must be set by IRT firmware to enable the IRT firmware debug.

When the DBG bit = ‘0’, there is no debug access to the IRT partition. CPU breakpoints and debugger memory accesses are disabled during IRT execution. IRT partition access is only enabled (PLCK bit = ‘0’) during IRT execution. When the DBG bit = ‘1’, debug access to the IRT partition is enabled. CPU breakpoints and debugger memory accesses are allowed during IRT execution. IRT partition access is enabled (PLCK bit = ‘0’) when the device resets into Debug mode.

The DONE bit is set by the IRT (or other root of trust) firmware upon completion of root of trust execution. The IRT partition is locked (PLCK bit = ‘1’) when the DONE bit is set, and there is a subsequent instruction fetch from the user program Flash not within an IRT region. This includes an attempted instruction fetch which has an error, such as an access privilege violation or an uncorrectable bit error. The PLCK bit is a read-only bit that indicates if the IRT partition is locked (access disabled). If the PLCK bit = ‘1’, access to IRT regions is disabled and the IRTCTRL and IRTSTAT registers are read- only.