15.2.1 Peripheral Clock Divider

To support multiple peripheral bus speeds, the CPU clock from CLKGEN1 is further divided to provide two additional clock speeds: standard and slow. The fast-speed peripheral clock FPB is the same as the CPU, the standard-speed peripheral clock (FPB/2), and the slow-speed peripheral clock is one-quarter speed of the peripheral clock (FPB/4), as shown in Figure 15-3.