19.1 Device-Specific Information

Table 19-1. DAC Summary
DAC Module Instances	Inputs per Instance	DAC Outputs	Clock Source	Peripheral Bus Speed
3	4	1	CLKGEN7	Standard

Table 19-2. High-Speed Analog Comparator Module Availability
DAC Input	28-Pin	36-Pin	48-Pin	64-Pin	PPS
CMP1A	x	x	x	x	No
CMP1B	x	x	x	x	No
CMP1C	x	x	x	x	No
CMP1D	x	x	x	x	No
CMP2A	x	x	x	x	No
CMP2B	x	x	x	x	No
CMP2C	x	x	x	x	No
CMP2D	x	x	x	x	No
CMP3A		x	x	x	No
CMP3B		x	x	x	No
CMP3C	x	x	x	x	No
CMP3D	x	x	x	x	No

Table 19-3. Slope Start Signal Selection (SLPSTRT)
Slope Start Signal Selection	Source
5-15	1
4	PWM4 Trigger 1
3	PWM3 Trigger 1
2	PWM2 Trigger 1
1	PWM1 Trigger 1
0	0

Table 19-4. Slope Stop A Signal Select bits (SLPSTOPA)
Slope Stop A Signal Selection	Source
5 - 15	1
4	PWM4 Trigger 2
3	PWM3 Trigger 2
2	PWM2 Trigger 2
1	PWM1 Trigger 2
0	0

Table 19-5. Slope Stop B Signal Select bits (SLPSTOPB)
Slope Stop B Signal Selection	Source
2 - 15	1
1	CMP1 Out
0	0

Table 19-6. Hysteretic Comparator Function Input Select Bits (HCFSEL)
Hysterectic Comparator Function Input Selection	Description
15	1
5 - 14	0
4	PWM4
3	PWM3
2	PWM2
1	PWM1
0	0

The calibration register FPDMDAC is located in Flash at 0x7F20B0 with the POSINLADJ, NEGINLADJ and DNLADJ bit fields. The location should be copied and written to the corresponding bit fields in the DACCTRL1 SFR at start-up.

Table 19-7. FPDMDAC Calibration Register
Name	Address Offset	Bit Field	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
FPDMDAC	0x0B0	31:24	Reserved	—	—	—	CFG_DAC_FILTER[3:0]
		23:16	—	—	POSINLADJ[5:0]
		15:8	—	NEGINLADJ[6:0]
		7:0	—	—	—	DNLADJ[4:0]

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