7.1.2 Multiple Speed Peripheral Bus and Clock Overview

The PIC32AK1216GC41064 family of devices implements a multiple-speed peripheral bus. Infrequent access and initialization SFRs are on the slow bus, whereas critical control loop type SFRs run at full speed relative to the CPU.

Each peripheral bus speed includes an associated peripheral clock. The peripheral bus SFR access and peripheral clock speed are equal, and are arranged in fast (1:1), standard (1/2) and slow speeds (1/4). The fast peripheral clock is equal to the CPU or system clock provided by CLKGEN1. The other two speeds are generated by the peripheral clock divider discussed in Peripheral Clock Divider.

Table 7-1 maps peripherals to their associated peripheral buses and clock speeds.

Table 7-1. Peripheral Bus Speed to Peripheral Mapping
Fast Speed Bus PeripheralsStandard Speed Bus PeripheralsSlow Speed Bus Peripherals
CPU PWMFlash NVM
Interrupt ControllerUARTClock monitors
GPIO(1)SPIWDT
CRCI2CPTG
Security ModuleSENTECC
Bus Matrix ControlQEIGPIO, PPS(2)
ADCCCPDMT
DAC and CMPPMD
Timer 1CLC
Performance monitorOp amps
Peripheral access controller
IO Integrity monitor
BISS
DMA
Note:
  1. Includes only PORT, LAT, TRIS and change notification registers.
  2. Includes remainder of GPIO registers.