12.2 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x3197 | Reserved | |||||||||
| 0x3198 | RCON | 7:0 | EXTR | SWR | WDTO | SLEEP | IDLE | BOR | POR | |
| 15:8 | CM | |||||||||
| 23:16 | VREG3R | VREG2R | VREG1R | |||||||
| 31:24 |
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x3197 | Reserved | |||||||||
| 0x3198 | RCON | 7:0 | EXTR | SWR | WDTO | SLEEP | IDLE | BOR | POR | |
| 15:8 | CM | |||||||||
| 23:16 | VREG3R | VREG2R | VREG1R | |||||||
| 31:24 |
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