8.2 Architectural Overview

This section describes the features of the data memory. PIC32AK1216GC41064 devices have a 16 Kbyte data memory space. Figure 8-1 shows a typical memory map for PIC32AK1216GC41064 family devices.

The PIC32AK1216GC41064 family of devices implements X and Y RAM in equal sizes. RAM width is 32-bit in addition to seven parity bits to implement ECC. The DEBUGRAM is 512 bytes.

Figure 8-1. Data Memory Map for PIC32AK1216GC41064 Family Devices
Note:
  1. Memory areas are not shown to scale.
  2. The PIC32AK1216GC41064 devices will have a unified memory map with non-overlapping Program and Data address spaces as shown in Figure 8-1. The address space is 8 MB total starting at 000000 and ending at 0x7CFFFF.

SFR space and data RAM are mapped starting at address 000000 to allow near memory access from instructions that can encode a memory address. The near address range for most file register instructions is 64KB total. The SFR space is 16 KB and is separated into different clock speeds via a peripheral bus splitter:

  • The address range 000000 - 0007FF is associated with a fast (1:1 System Clock) peripheral bus. A minimum number of SFRs are mapped into this region.
  • The address range 000800 - 002FFF is associated with the standard speed (1:2 or slower) peripheral bus. The majority of the peripheral SFRs will be mapped into this region.
  • The address range 003000 - 003FFF is associated with the slow speed (1:4 or slower) peripheral bus. Peripheral SFRs that require infrequent access will be mapped into this region.
  • The address range 7C0000 - 7CFFFF is associated with the slow speed (1:4 or slower) peripheral bus dedicated to the calibration and configuration registers in “far” memory space.