28.5 CLC Application Example

Figure 28-4 depicts the configuration of CLC to generate Frequency Shift Key (FSK) modulation on a UART signal using CLC.

Figure 28-4. CLC Configuration for FSK Generation
Note: Inverter operation shown in the figure is done using the CLC register bits.
The peripherals required for this application are:
  • CLC1 and CLC2
  • UART data as modulator signal
  • Peripheral clock to modulate logic ‘1’
  • LPRC to modulate logic ‘0’
Note: UART, system clock and LPRC are used as examples for the modulator signal and carrier signal, respectively. However, it is possible to choose other sources as modulator and carrier signals.

The following is the application code for FSK modulation of the UART data.

FSK Modulation of UART Data

/*Select input source for CLC1*/
CLC1SELbits.DS1 = 1;   //Peripheral clock as input source to modulate high signal
CLC1SELbits.DS2 = 3;   //UART TX data as input source
CLC1SELbits.DS4 = 1;   //CLC2 output as input source

 //Configure Gates of CLC1
CLC1GLSbits.G2D2T = 1; // Gate 2 selects Data 2 (here UART TX data)
CLC1GLSbits.G1D1T = 1; // Gate 1 selects Data 1(here peripheral clock)
CLC1GLSbits.G3D2N = 1; // Gate 3 selects inverted Data 2 (here UART TX data)
CLC1GLSbits.G4D4T = 1; // Gate 4 selects Data 4 (here CLC2 output)

/*Select input source for CLC2*/
CLC2SELbits.DS1 = 3;   //LPRC as input source to modulate logic low signal

 //Configure Gates of CLC2
CLC2GLSbits.G1D1T = 1; // All gates select data 1 as input (here LPRC)
CLC2GLSbits.G2D1T = 1;
CLC2GLSbits.G3D1T = 1; 
CLC2GLSbits.G4D1T = 1;

 //Configure CLC1 mode and output
CLC1CONbits.LCOE = 1;  // Enable CLC output on IO
CLC1CONbits.MODE = 0;  // Select AND-OR logic function

 //Configure CLC2 mode and output
CLC2CONbits.LCOE = 1;  // Enable CLC output on IO
CLC2CONbits.MODE = 2;  // Select AND logic function


/* UART configuration goes here*/

 //Turn on CLCs
CLC1CONbits.ON = 1;  // Enable CLC1
CLC2CONbits.ON = 1;  // Enable CLC2

/*Turn on UART here*/