28.5.1 Control A


Bit	7	6	5	4	3	2	1	0
	ENABLE		FIFOEN	STFRNUM	MAXEP[3:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		0	0	0	0	0	0

Bit 7 – ENABLE USB Enable

Writing a ‘1’ to this bit enables the USB peripheral.

Writing a ‘0’ to this bit disables the USB peripheral and immediately aborts ongoing transactions.

Value	Description
1	The USB peripheral is enabled
0	The USB peripheral is disabled

Bit 5 – FIFOEN Transaction Complete FIFO Enable

Value	Description
1	The USB Transaction Complete FIFO (FIFO) is enabled. The FIFO stores the offset to the endpoint configuration table address of each endpoint that generates a transaction complete interrupt.
0	The FIFO is disabled and the RAM allocated for it is freed

Bit 4 – STFRNUM Store Frame Number Enable

This bit controls whether storing the last SOF token frame number in the Frame Number (FRAMENUM) register is enabled.

Value	Description
1	Storing the last SOF token frame number in FRAMENUM is enabled
0	Storing the last SOF token frame number in FRAMENUM is disabled

Bits 3:0 – MAXEP[3:0] Maximum Endpoint Address

This bit field selects the number of endpoint addresses used by the USB peripheral. Incoming packets with a higher endpoint number than this address will be discarded. Packets with an endpoint address lower than or equal to this address will cause the USB peripheral to look up the addressed endpoint in the endpoint configuration table. Example: If EP 0, 1 and 2 are used, set this field to 2.

Name:	CTRLA
Offset:	0x0
Reset:	0x00