28.5.11 Interrupt Flags B

If FIFO is disabled This flag is set when the Transaction Complete (TRNCOMPL) flag in the Endpoint Status (EPn.STATUS) register is set while the Transaction Complete Interrupt Disable (TCDSBL) bit in the Endpoint Control (EPn.CTRL) register is ‘0’. Writing a ‘1’ to this bit will clear this flag.

If FIFO is enabled This flag is set when there are unread elements in the FIFO. This flag is cleared when the last element has been read from the FIFO so that the FIFO is empty, i.e., the FIFO Read Pointer is equal to the FIFO Write Pointer.

This flag is set by an RMW operation initiated by writing to an RMW register. This flag is intended to be polled and does not have a corresponding Interrupt Enable bit in INTCTRLB. The RMW registers must not be written when this flag is set.

This flag is set when the Global NACK has been made effective, i.e., has propagated through the USB logic, and its effects can be seen on the USB bus. The flag is not set if Automatic GNACK (GNAUTO) is configured in the Control B (CTRLB) register.

This flag is set when a SETUP transaction has successfully completed.

Writing a ‘1’ to this bit will clear the flag.