28.5.7 Endpoint Configuration Table Pointer
| Name: | EPPTR |
| Offset: | 0x6 |
| Reset: | 0x00 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EPPTR[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EPPTR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – EPPTR[15:0] Endpoint Configuration Table Pointer
This bit field specifies the RAM address where the endpoint configuration table is located. The pointer to the endpoint configuration table must be aligned to a 16-bit word, i.e., EPPTR[0] must be zero. Only the number of bits required to address the device’s available internal RAM is implemented. Unused bits will always read as zero.