37.7 I/O Pins

General I/O Pins

Table 37-6. I/O Pin Specifications
Symbol	Description	Min.	Typ.✝	Max.	Unit	Conditions
Input Low Voltage
V_IL	I/O PORT:
	with Schmitt Trigger buffer	—	—	0.2×V_DD	V	INLVL selecting `ST`⁽¹⁾
	with I²C levels	—	—	0.3×V_DD	V
	with SMBus 3.0 levels	—	—	0.8	V
	with LVBUF (TTL compatible)	—	—	0.9	V	INLVL selecting `TTL`⁽¹⁾
	RESET pin	—	—	0.2×V_DD	V
Input High Voltage
V_IH	I/O PORT:
	with Schmitt Trigger buffer	0.8×V_DD	—	—	V
	with I²C levels	0.7×V_DD	—	—	V
	with SMBus 3.0 levels	1.35	—	—	V	0°C ≤ T_A ≤ +85°C, 2.5V ≤ V_DD ≤ 5.5V
	with SMBus 3.0 levels	1.45	—	—	V	-40°C ≤ T_A ≤ +85°C, 1.8V ≤ V_DD ≤ 5.5V
	with LVBUF (TTL compatible)	1.2	—	—	V
	RESET Pin	0.8×V_DD	—	—	V
Input Leakage Current⁽²⁾
I_IL	I/O PORTS	—	±5	±125	nA	GND ≤ V_PIN ≤ V_DD, pin at high-impedance, T_A = 85°C
I_IL	RESET Pin⁽³⁾	—	±50	±200	nA	GND ≤ V_PIN ≤ V_DD, pin at high-impedance, T_A = 85°C
Pull-up Current
I_PUR		—	150	200	μA	V_DD = 3.0V, V_PIN = GND
Output Low Voltage
V_OL	Standard I/O ports	—	—	0.6	V	I_OL = 10 mA, V_DD = 3.0V
Output High Voltage
V_OH	Standard I/O ports	V_DD-0.7	—	—	V	I_OH = 6 mA, V_DD = 3.0V
I/O Rise Time
t_SR	Rising	—	45	—	ns	PORTCTRL.SRL = `0x01`
	Rising	—	22	—	ns	PORTCTRL.SRL = `0x00`
	Falling	—	30	—	ns	PORTCTRL.SRL = `0x01`
	Falling	—	16	—	ns	PORTCTRL.SRL = `0x00`
Pin Capacitance
C_IO	All I/O pins	—	5	—	pF
✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested. Note: The Input Level Select (INLVL) bit is configured in the PORT peripheral by writing either the PORTx.PINCONFIG register or the PORTx.PINnCTRL register. The negative current is defined as the current sourced by the pin. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.

USB Pins

Table 37-7. USB Pin Specifications
Symbol	Description	Min.	Typ.✝	Max.	Unit	Conditions
Input Leakage Current⁽¹⁾
I_ILUD	Input leakage on USB data pins DM	—	±5	±125	nA	GND ≤ V_PIN ≤ V_DD, pin at high-impedance, T_A= 85°C
I_ILUD	Input leakage on USB data pins DP	—	±5	±125	nA	GND ≤ V_PIN ≤ V_DD, pin at high-impedance, T_A= 85°C
I/O Rise Time
	DP rising	—	13	—	ns
	DM rising	—	13	—	ns
	DP falling	—	14	—	ns
	DM falling	—	14	—	ns
Input Capacitance
C_UD	Input capacitance on USB data pins DM	—	15	100	pF	pin at high-impedance
C_UD	Input capacitance on USB data pins DP	—	15	100	pF	pin at high-impedance
✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. Load condition is 50 pF. These parameters are for design guidance only and are not tested. Note: The negative current is defined as the current sourced by the pin. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.