37.7 I/O Pins

General I/O Pins

Table 37-6. I/O Pin Specifications
Symbol Description Min. Typ.✝ Max. Unit Conditions
Input Low Voltage
VIL I/O PORT:
  • with Schmitt Trigger buffer
 — — 0.2×VDD V INLVL selecting ST(1)
  • with I2C levels
 — — 0.3×VDD V
  • with SMBus 3.0 levels
 — — 0.8 V
  • with LVBUF (TTL compatible)
 — — 0.9 V INLVL selecting TTL(1)
RESET pin — — 0.2×VDD V
Input High Voltage
VIH I/O PORT:
  • with Schmitt Trigger buffer
 0.8×VDD — — V
  • with I2C levels
 0.7×VDD — — V
  • with SMBus 3.0 levels
 1.35 — — V

0°C ≤ TA ≤ +85°C,

2.5V ≤ VDD ≤ 5.5V
1.45 — — V

-40°C ≤ TA ≤ +85°C,

1.8V ≤ VDD ≤ 5.5V
  • with LVBUF (TTL compatible)
 1.2 — — V
RESET Pin 0.8×VDD — — V
Input Leakage Current(2)
IIL I/O PORTS — ±5 ±125 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA = 85°C
RESET Pin(3) — ±50 ±200 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA = 85°C
Pull-up Current
IPUR — 150 200 μA VDD = 3.0V, VPIN = GND
Output Low Voltage
VOL Standard I/O ports — — 0.6 V IOL = 10 mA, VDD = 3.0V
Output High Voltage
VOH Standard I/O ports VDD-0.7 — — V IOH = 6 mA, VDD = 3.0V
I/O Rise Time
tSR Rising — 45 — ns PORTCTRL.SRL = 0x01
Rising — 22 — ns PORTCTRL.SRL = 0x00
Falling — 30 — ns PORTCTRL.SRL = 0x01
Falling — 16 — ns PORTCTRL.SRL = 0x00
Pin Capacitance
CIO All I/O pins — 5 — pF

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

Note:
  1. The Input Level Select (INLVL) bit is configured in the PORT peripheral by writing either the PORTx.PINCONFIG register or the PORTx.PINnCTRL register.
  2. The negative current is defined as the current sourced by the pin.
  3. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.

USB Pins

Table 37-7. USB Pin Specifications
Symbol Description Min. Typ.✝ Max. Unit Conditions
Input Leakage Current(1)
IILUD Input leakage on USB data pins DM — ±5 ±125 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C
Input leakage on USB data pins DP — ±5 ±125 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C
I/O Rise Time
DP rising — 13 — ns
DM rising — 13 — ns
DP falling — 14 — ns
DM falling — 14 — ns
Input Capacitance
CUD Input capacitance on USB data pins DM — 15 100 pF pin at high-impedance
Input capacitance on USB data pins DP — 15 100 pF pin at high-impedance

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. Load condition is 50 pF. These parameters are for design guidance only and are not tested.

Note:
  1. The negative current is defined as the current sourced by the pin.
  2. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.