37.16 ADC

Table 37-22. ADC Accuracy Specifications
Operating Conditions:
  • VADCREF = 3.0V
  • ADC in 10-bit, single ended conversion mode
  • fCLK_ADC = 1 MHz
Symbol Description Min. Typ. ✝ Max. Unit Conditions
NR Resolution 10 bit
EINL Integral nonlinearity error -1.8 0.1 1.8 LSb
EDNL Differential nonlinearity error(1) -1 0.1 1 LSb
EOFF Offset error 0 2.5 5 LSb
EGAIN Gain error -5 1.5 5 LSb
VADCREF * ADC reference voltage 1.024 VDD V fCLK_ADC ≤ 500 kHz
1.8 VDD V
VAIN Full-scale range GND VADCREF V
ZAIN Recommended impedance of analog voltage source 10
RVREFA ADC voltage reference ladder impedance(2) 50

VDD/10 divider accuracy
(VDDDIV10)

±10 % Measured with ADC using on-chip internal reference

Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

* These parameters are characterized but not tested in production.

Note:
  1. The ADC conversion result never decreases with an increase in the input and has no missing codes.
  2. This is the impedance seen by the VREFA pin when the external reference is selected.
Table 37-23. ADC Conversion Timing Specifications
Symbol Description Min. Typ. ✝ Max. Unit Conditions
TCLK_ADC * ADC clock period 0.5 8 μs
tCNV Conversion time 11.5TCLK_ADC + 2TCLK_PER
fADC * Sample rate 8 170 ksps CLK_PER=24 MHz
tSENSE * Delay for changing MUXPOS to TEMP 40 μs
tADC_INIT * Initialization time 6 μs

Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

* These parameters are characterized but not tested in production.