fSSCK
(1) |
Client SCK clock frequency |
— |
— |
fCLK_PER/6 |
MHz |
|
TSSCK
(1) |
Client SCK period |
6×TCLK_PER |
— |
— |
ns |
|
tSSCKW
(1) |
SCK high/low width |
3×TCLK_PER
|
— |
— |
ns |
|
tSIS
(1) |
MOSI setup to SCK |
0 |
— |
— |
ns |
|
tSIH
(1) |
MOSI hold after SCK |
3×TCLK_PER
|
— |
— |
ns |
|
tSSS
(1) |
SS low before SCK |
TCLK_PER |
— |
— |
ns |
|
tSSH
(1) |
SS high after SCK |
TCLK_PER |
— |
— |
ns |
|
tSOS |
MISO valid after SCK |
— |
tSR
(2) |
— |
ns |
fSSCK≥fCLK_PER/6 |
— |
— |
— |
fSSCK<fCLK_PER/6 |
tSOSS |
MISO setup after SS low |
— |
tSR
(2) |
— |
ns |
|
tSOSH |
MISO hold after SS low |
— |
tSR
(2) |
— |
ns |
|
- These parameters are characterized but not tested in production.
- tSR is the I/O pin rise time.
|