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PolarFire FPGA Transceiver Decision Feedback Equalization AN4950
PolarFire FPGA Transceiver Decision Feedback Equalization AN4950
  1. Home
  2. 4 Demo Design
  3. 4.1 Design Implementation
  4. 4.1.2 CoreABC
  5. 4.1.2.1 CoreABC Program
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AN4950

  • Introduction
  • 1 DFE Calibration
  • 2 Design Requirements
  • 3 Prerequisites
  • 4 Demo Design
    • 4.1 Design Implementation
      • 4.1.1 PF_CCC_0 Configuration
      • 4.1.2 CoreABC
        • 4.1.2.1 CoreABC Program
      • 4.1.3 Dynamic Reconfiguration Interface
      • 4.1.4 Transceiver Interface Reconfiguration
      • 4.1.5 PolarFire Transceiver Reference Clock
      • 4.1.6 Transmit PLL
      • 4.1.7 Flag_for_RXPLL_Lock
      • 4.1.8 PRBS Generator and Checker
    • 4.2 Port Description
    • 4.3 Clocking Structure
    • 4.4 Reset Structure
  • 5 Libero Design Flow
  • 6 Running the Demo
  • 7 Appendix 1: Programming the Device Using FlashPro Express
  • 8 Appendix 2: Running the Tcl Script
  • 9 Revision History
  • Microchip FPGA Support
  • Microchip Information

4.1.2.1 CoreABC Program

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The following figure illustrates the register settings required for performing DFE calibration.

Important: The register address changes depending on the transceiver Quad and Lanes used. In this demo, Q2 Lane0 is used. For more information, see PolarFire Device Register Map and PolarFire SoC Device Register Map.
Figure 4-5. CoreABC Program

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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