ATWILC1000-MR110xB

4.6.2 SDIO Timing

The SDIO client interface timing is shown in the following figure.

Figure 4-2. SDIO Timing Diagram

SDIO client timing parameters are provided in the following table.

Table 4-7. SDIO Timing Parameters
Parameter	Symbol	Min	Max	Units
Clock Input Frequency⁽¹⁾	f_PP	0	50	MHz
Clock Low Pulse Width	t_WL	9	—	ns
Clock High Pulse Width	t_WH	4.5	—
Clock Rise Time	t_LH	0	5
Clock Fall Time	t_HL	0	5
Input Setup Time	t_ISU	6	—
Input Hold Time	t_IH	4	—
Output Delay⁽²⁾	t_ODLY	3	11

Maximum clock frequency specified is limited by the SDIO client interface internal design; the actual maximum clock frequency can be lower and depends on the specific PCB layout.
Timing is based on 15 pF output loading.

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