15.1.12 Velocity x Counter Hold Register

Name:	VELxHLD
Offset:	0x15A, 0x18E, 0xEDE


Bit	15	14	13	12	11	10	9	8
	VELHLD[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	VELHLD[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – VELHLD[31:16] Hold for Reading/Writing Velocity Counter Register (VELxCNT[31:16]) bits

DS70005496D

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.