15.15.1 Digital Interface Timing Characteristics

Note: This is for internal communication between the AT86RF212B transceiver and the SAM L21 microcontroller.

Test Conditions: TOP = +25°C, VDD = 3.0V, CLoad = 50pF (unless otherwise stated).

SymbolParameterConditionMin.Typ.Max.Unit
fsyncSCLK frequencySynchronous operation 8MHz
fasyncSCLK frequencyAsynchronous operation 7.5MHz
t1/SEL falling edge to MISO active 180ns
t2SCLK falling edge to MISO outData hold time25 ns
t3MOSI setup time 10 ns
t4MOSI hold time 10 ns
t5LSB last byte to MSB next byte 250(1) ns
t6/SEL rising edge to MISO tri state 10ns
t7SLP_TR pulse widthTX start trigger62.5 Note(2)ns
t8SPI idle time: SEL rising to falling edge

SPI read/write, standard SRAM and frame access modes

Idle time between consecutive SPI accesses

250 ns
t8aSPI idle time: SEL rising to falling edge

Fast SRAM read/write access mode

Idle time between consecutive SPI accesses

500 ns
t9SCLK rising edge LSB to /SEL rising edge 250 ns
t10Reset pulse width≥ 10 clock cycles at 16MHz625 ns
t11SPI access latency after reset≥ 10 clock cycles at 16MHz625 ns
t12Dynamic frame buffer protection: IRQ latency 750 ns
tIRQIRQ_2, IRQ_3, IRQ_4 latencyRelative to the event to be indicated 9 µs
fCLKMOutput clock frequency at pin 17 (CLKM)

Configurable by the CLKM_CTRL bits in the TRX_CTRL 0 register (TRX_CTRL_0.CLKM_CTRL)

CLKM_CTRL = 0

0 MHz
CLKM_CTRL = 1 1 MHz
CLKM_CTRL = 2 2 MHz
CLKM_CTRL = 3 4 MHz
CLKM_CTRL = 4 8 MHz
CLKM_CTRL = 5 16 MHz
CLKM_CTRL = 6 250 kHz
CLKM_CTRL = 7(3) 20.0 kHz
CLKM_CTRL = 7(4) 40.0 kHz
CLKM_CTRL = 7(5) 25.0 kHz
CLKM_CTRL = 7(6) 62.5 kHz
  1. For Fast SRAM read/write accesses on address space 0x82 – 0x94 the time t5(Min.) and t8(Min.) increases to 500ns.
  2. Maximum pulse width less than (TX frame length + 16µs).
  3. 1/50MHz; Only in BPSK mode with fPSDU = 20kb/s.
  4. 1/25MHz; Only in BPSK mode with fPSDU = 40kb/s.
  5. 1/40MHz; Only in O-QPSK mode with fPSDU = 100/200/400kb/s.
  6. 1/16MHz; Only in O-QPSK mode with fPSDU = 250/500/1000kb/s.