46.10.34 USART LON Mode Register

This register is relevant only if USART_MODE = 0x9 in the USART Mode Register.

This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.

Name: FLEX_US_LONMR
Offset: 0x260
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 EOFS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   LCDSDMAMCDTAILTCOLCOLDETCOMMT 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 23:16 – EOFS[7:0] End of Frame Condition Size

ValueDescription
0–255

Defines the minimum transitionless time for the IP to detect a LON end of frame condition.

teof = (EOFS+1) × tclock × 8 × (2- OVER)

Bit 5 – LCDS LON Collision Detection Source

ValueDescription
0

LON collision detection source is external.

1

LON collision detection source is internal.

Bit 4 – DMAM LON DMA Mode

ValueDescription
0

The LON data length register FLEX_US_LONDL is not written by the DMA.

1

The LON data length register FLEX_US_LONDL is written by the DMA.

Bit 3 – CDTAIL LON Collision Detection on Frame Tail

ValueDescription
0

Detect collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode.

1

Ignore collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode.

Bit 2 – TCOL Terminate Frame upon Collision Notification

ValueDescription
0

Do not terminate the frame in LON comm_type = 1 mode upon collision detection.

1

Terminate the frame in LON comm_type = 1 mode upon collision detection if possible.

Bit 1 – COLDET LON Collision Detection Feature

ValueDescription
0

LON collision detection feature disabled.

1

LON collision detection feature enabled.

Bit 0 – COMMT LON comm_type Parameter Value

ValueDescription
0

LON comm_type = 1 mode.

1

LON comm_type = 2 mode.