This configuration is relevant only if USART_MODE = 0x9 in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
Name:
FLEX_US_IDR (LON_MODE)
Offset:
0x20C
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
LBLOVFE
LRXD
LFET
LCOL
LTXD
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
UNRE
TXEMPTY
Access
W
W
Reset
–
–
Bit
7
6
5
4
3
2
1
0
LCRCE
LSFE
OVRE
TXRDY
RXRDY
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit 28 – LBLOVFE LON Backlog Overflow Error Interrupt
Disable
Bit 27 – LRXD LON Reception Done Interrupt
Disable
Bit 26 – LFET LON Frame Early Termination Interrupt
Disable
Bit 25 – LCOL LON Collision Interrupt
Disable
Bit 24 – LTXD LON Transmission Done Interrupt
Disable
Bit 10 – UNRE Underrun Error Interrupt
Disable
Bit 9 – TXEMPTY TXEMPTY Interrupt
Disable
Bit 7 – LCRCE LON CRC Error Interrupt
Disable
Bit 6 – LSFE LON Short Frame Error Interrupt
Disable
Bit 5 – OVRE Overrun Error Interrupt
Disable
Bit 1 – TXRDY TXRDY Interrupt
Disable
Bit 0 – RXRDY RXRDY Interrupt
Disable
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