This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
Name:
FLEX_US_IDR (LIN_MODE)
Offset:
0x20C
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
LINHTE
LINSTE
LINSNRE
LINCE
LINIPE
LINISFE
LINBE
Access
W
W
W
W
W
W
W
Reset
–
–
–
–
–
–
–
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
LINTC
LINID
LINBK
TXEMPTY
TIMEOUT
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
TXRDY
RXRDY
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit 31 – LINHTE LIN Header Timeout Error Interrupt
Disable
Bit 30 – LINSTE LIN Synch Tolerance Error Interrupt
Disable
Bit 29 – LINSNRE LIN Client Not Responding Error Interrupt
Disable
Bit 28 – LINCE LIN Checksum Error Interrupt
Disable
Bit 27 – LINIPE LIN Identifier Parity Interrupt
Disable
Bit 26 – LINISFE LIN Inconsistent Synch Field Error Interrupt
Disable
Bit 25 – LINBE LIN Bus Error Interrupt
Disable
Bit 15 – LINTC LIN Transfer Completed Interrupt
Disable
Bit 14 – LINID LIN Identifier Sent or LIN Identifier
Received Interrupt Disable
Bit 13 – LINBK LIN Break Sent or LIN Break Received
Interrupt Disable
Bit 9 – TXEMPTY TXEMPTY Interrupt
Disable
Bit 8 – TIMEOUT Timeout Interrupt
Disable
Bit 7 – PARE Parity Error Interrupt
Disable
Bit 6 – FRAME Framing Error Interrupt
Disable
Bit 5 – OVRE Overrun Error Interrupt
Disable
Bit 1 – TXRDY TXRDY Interrupt
Disable
Bit 0 – RXRDY RXRDY Interrupt
Disable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
