46.10.37 USART LON L2HDR Register
This register is relevant only if USART_MODE = 0x9 in the USART Mode Register.
| Name: | FLEX_US_LONL2HDR |
| Offset: | 0x26C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PB | ALTP | BLI[5:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – PB LON Priority Bit
| Value | Description |
|---|---|
| 0 | LON priority bit reset. |
| 1 | LON priority bit set. |
Bit 6 – ALTP LON Alternate Path Bit
| Value | Description |
|---|---|
| 0 | LON alternate path bit reset. |
| 1 | LON alternate path bit set. |
Bits 5:0 – BLI[5:0] LON Backlog Increment
| Value | Description |
|---|---|
| 0–63 | LON backlog increment to be generated as a result of delivering the LON frame. |