46.10.16 USART Channel Status Register (LIN_MODE)

This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register.

Name: FLEX_US_CSR (LIN_MODE)
Offset: 0x214
Reset: 
Property: Read-only

Bit 3130292827262524 
 LINHTELINSTELINSNRELINCELINIPELINISFELINBE  
Access RRRRRRR 
Reset  
Bit 2322212019181716 
 LINBLS        
Access R 
Reset  
Bit 15141312111098 
 LINTCLINIDLINBK   TXEMPTYTIMEOUT 
Access RRRRR 
Reset  
Bit 76543210 
 PAREFRAMEOVRE   TXRDYRXRDY 
Access RRRRR 
Reset  

Bit 31 – LINHTE LIN Header Timeout Error

ValueDescription
0 No LIN header timeout error has been detected since the last RSTSTA command was issued.
1 A LIN header timeout error has been detected since the last RSTSTA command was issued.

Bit 30 – LINSTE LIN Synch Tolerance Error

ValueDescription
0 No LIN synch tolerance error has been detected since the last RSTSTA command was issued.
1 A LIN synch tolerance error has been detected since the last RSTSTA command was issued.

Bit 29 – LINSNRE LIN Client Not Responding Error

ValueDescription
0 No LIN client not responding error has been detected since the last RSTSTA command was issued.
1 A LIN client not responding error has been detected since the last RSTSTA command was issued.

Bit 28 – LINCE LIN Checksum Error

ValueDescription
0 No LIN checksum error has been detected since the last RSTSTA command was issued.
1 A LIN checksum error has been detected since the last RSTSTA command was issued.

Bit 27 – LINIPE LIN Identifier Parity Error

ValueDescription
0 No LIN identifier parity error has been detected since the last RSTSTA command was issued.
1 A LIN identifier parity error has been detected since the last RSTSTA command was issued.

Bit 26 – LINISFE LIN Inconsistent Synch Field Error

ValueDescription
0 No LIN inconsistent synch field error has been detected since the last RSTSTA
1 The USART is configured as a client node and a LIN Inconsistent synch field error has been detected since the last RSTSTA command was issued.

Bit 25 – LINBE LIN Bit Error

ValueDescription
0 No bit error has been detected since the last RSTSTA command was issued.
1 A bit error has been detected since the last RSTSTA command was issued.

Bit 23 – LINBLS LIN Bus Line Status

ValueDescription
0 LIN bus line is set to 0.
1 LIN bus line is set to 1.

Bit 15 – LINTC LIN Transfer Completed

ValueDescription
0 The USART is idle or a LIN transfer is ongoing.
1 A LIN transfer has been completed since the last RSTSTA command was issued.

Bit 14 – LINID LIN Identifier Sent or LIN Identifier Received

If USART operates in LIN Host mode (USART_MODE = 0xA):

0: No LIN identifier has been sent since the last RSTSTA command was issued.

1: At least one LIN identifier has been sent since the last RSTSTA command was issued.

If USART operates in LIN Client mode (USART_MODE = 0xB):

0: No LIN identifier has been received since the last RSTSTA command was issued.

1: At least one LIN identifier has been received since the last RSTSTA.

Bit 13 – LINBK LIN Break Sent or LIN Break Received

Applicable if USART operates in LIN Host mode (USART_MODE = 0xA):

0: No LIN break has been sent since the last RSTSTA command was issued.

1: At least one LIN break has been sent since the last RSTSTA.

If USART operates in LIN Client mode (USART_MODE = 0xB):

0: No LIN break has received sent since the last RSTSTA command was issued.

1: At least one LIN break has been received since the last RSTSTA command was issued.

Bit 9 – TXEMPTY Transmitter Empty (cleared by writing FLEX_US_THR)

ValueDescription
0 There are characters in either FLEX_US_THR or the Transmit Shift Register, or the transmitter is disabled.
1 There are no characters in FLEX_US_THR, nor in the Transmit Shift Register.

Bit 8 – TIMEOUT Receiver Timeout

ValueDescription
0 There has not been a timeout since the last start timeout command (FLEX_US_CR.STTTO) or the Timeout Register is 0.
1 There has been a timeout since the last start timeout command (FLEX_US_CR.STTTO).

Bit 7 – PARE Parity Error

ValueDescription
0 No parity error has been detected since the last RSTSTA command was issued.
1 At least one parity error has been detected since the last RSTSTA command was issued.

Bit 6 – FRAME Framing Error

ValueDescription
0 No stop bit has been detected low since the last RSTSTA command was issued.
1 At least one stop bit has been detected low since the last RSTSTA command was issued.

Bit 5 – OVRE Overrun Error

ValueDescription
0 No overrun error has occurred since the last RSTSTA command was issued.
1 At least one overrun error has occurred since the last RSTSTA command was issued.

Bit 1 – TXRDY Transmitter Ready (cleared by writing FLEX_US_THR)

ValueDescription
0 A character in FLEX_US_THR is waiting to be transferred to the Transmit Shift Register, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1 There is no character in FLEX_US_THR.

Bit 0 – RXRDY Receiver Ready (cleared by reading FLEX_US_RHR)

ValueDescription
0 No complete character has been received since the last read of FLEX_US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1 At least one complete character has been received and FLEX_US_RHR has not yet been read.