This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name:
FLEX_US_IMR (LIN_MODE)
Offset:
0x210
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
LINHTE
LINSTE
LINSNRE
LINCE
LINIPE
LINISFE
LINBE
Access
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
LINTC
LINID
LINBK
TXEMPTY
TIMEOUT
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
TXRDY
RXRDY
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 31 – LINHTE LIN Header Timeout Error Interrupt
Mask
Bit 30 – LINSTE LIN Synch Tolerance Error Interrupt
Mask
Bit 29 – LINSNRE LIN Client Not Responding Error Interrupt
Mask
Bit 28 – LINCE LIN Checksum Error Interrupt
Mask
Bit 27 – LINIPE LIN Identifier Parity Interrupt
Mask
Bit 26 – LINISFE LIN Inconsistent Synch Field Error Interrupt
Mask
Bit 25 – LINBE LIN Bus Error Interrupt
Mask
Bit 15 – LINTC LIN Transfer Completed Interrupt
Mask
Bit 14 – LINID LIN Identifier Sent or LIN Identifier
Received Interrupt Mask
Bit 13 – LINBK LIN Break Sent or LIN Break Received
Interrupt Mask
Bit 9 – TXEMPTY TXEMPTY Interrupt
Mask
Bit 8 – TIMEOUT Timeout Interrupt
Mask
Bit 7 – PARE Parity Error Interrupt
Mask
Bit 6 – FRAME Framing Error Interrupt
Mask
Bit 5 – OVRE Overrun Error Interrupt
Mask
Bit 1 – TXRDY TXRDY Interrupt
Mask
Bit 0 – RXRDY RXRDY Interrupt
Mask
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