28.7.12 Debouncer Enable
Important: For PIC32CM LS00/LS60 Non-Secure accesses, read and
write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as
Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Some restrictions apply for the
Non-Secure accesses to an Enable-Protected register as it will not be possible for the
Non-Secure to configure it once this register is enabled by the Secure application. This
will require some veneers to be implemented on Secure side.
| Name: | DEBOUNCEN |
| Offset: | 0x30 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected, Mix-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DEBOUNCEN15 | DEBOUNCEN14 | DEBOUNCEN13 | DEBOUNCEN12 | DEBOUNCEN11 | DEBOUNCEN10 | DEBOUNCEN9 | DEBOUNCEN8 | ||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DEBOUNCEN7 | DEBOUNCEN6 | DEBOUNCEN5 | DEBOUNCEN4 | DEBOUNCEN3 | DEBOUNCEN2 | DEBOUNCEN1 | DEBOUNCEN0 | ||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – DEBOUNCEN Debouncer Enable
The bit x of DEBOUNCEN set the Debounce mode for the interrupt associated with the EXTINTx pin.
| Value | Description |
|---|---|
| 0 | The EXTINT x edge input is not debounced. |
| 1 | The EXTINT x edge input is debounced. |