28.7.5 Event Control

Important: For PIC32CM LS00/LS60 Non-Secure accesses, read and write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Some restrictions apply for the Non-Secure accesses to an Enable-Protected register as it will not be possible for the Non-Secure to configure it once this register is enabled by the Secure application. This will require some veneers to be implemented on Secure side.
Name: EVCTRL
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Mix-Secure

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 EXTINTEO15EXTINTEO14EXTINTEO13EXTINTEO12EXTINTEO11EXTINTEO10EXTINTEO9EXTINTEO8 
Access RW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RW 
Reset 00000000 
Bit 76543210 
 EXTINTEO7EXTINTEO6EXTINTEO5EXTINTEO4EXTINTEO3EXTINTEO2EXTINTEO1EXTINTEO0 
Access RW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RW 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTEO External Interrupt Event Output Enable

The bit x of EXTINTEO enables the event associated with the EXTINTx pin.
ValueDescription
0 Event from pin EXTINTx is disabled.
1 Event from pin EXTINTx is enabled and will be generated when EXTINTx pin matches the external interrupt sensing configuration.