28.7.5 Event Control
Important: For PIC32CM LS00/LS60 Non-Secure accesses, read and
write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as
Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Some restrictions apply for the
Non-Secure accesses to an Enable-Protected register as it will not be possible for the
Non-Secure to configure it once this register is enabled by the Secure application. This
will require some veneers to be implemented on Secure side.
Name: | EVCTRL |
Offset: | 0x08 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection, Enable-Protected, Mix-Secure |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
EXTINTEO15 | EXTINTEO14 | EXTINTEO13 | EXTINTEO12 | EXTINTEO11 | EXTINTEO10 | EXTINTEO9 | EXTINTEO8 | ||
Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
EXTINTEO7 | EXTINTEO6 | EXTINTEO5 | EXTINTEO4 | EXTINTEO3 | EXTINTEO2 | EXTINTEO1 | EXTINTEO0 | ||
Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTEO External Interrupt Event Output Enable
Value | Description |
---|---|
0 | Event from pin EXTINTx is disabled. |
1 | Event from pin EXTINTx is enabled and will be generated when EXTINTx pin matches the external interrupt sensing configuration. |