28.7.9 External Interrupt Asynchronous Mode
Important: For PIC32CM LS00/LS60 Non-Secure accesses, read and
write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as
Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Some restrictions apply for the
Non-Secure accesses to an Enable-Protected register as it will not be possible for the
Non-Secure to configure it once this register is enabled by the Secure application. This
will require some veneers to be implemented on Secure side.
| Name: | ASYNCH |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected, Mix-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ASYNCH15 | ASYNCH14 | ASYNCH13 | ASYNCH12 | ASYNCH11 | ASYNCH10 | ASYNCH9 | ASYNCH8 | ||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ASYNCH7 | ASYNCH6 | ASYNCH5 | ASYNCH4 | ASYNCH3 | ASYNCH2 | ASYNCH1 | ASYNCH0 | ||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – ASYNCH Asynchronous Edge Detection Mode
The bit x of ASYNCH set the Asynchronous Edge Detection Mode for the interrupt associated with the EXTINTx pin.
| Value | Description |
|---|---|
| 0 | The EXTINT x edge detection is synchronously operated. |
| 1 | The EXTINT x edge detection is asynchronously operated. |