28.7.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits, Secure

Bit 76543210 
    CKSEL  ENABLESWRST 
Access RW/-/RWRW/-/RWW/-/W 
Reset 000 

Bit 4 – CKSEL Clock Selection

The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32.768 kHz is required for filtering) or by CLK_ULP32K (when power consumption is the priority).

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0 The EIC is clocked by GCLK_EIC.
1 The EIC is clocked by CLK_ULP32K.

Bit 1 – ENABLE Enable

Due to synchronization there is a delay between writing to CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register will be set (SYNCBUSY.ENABLE=1). SYNCBUSY.ENABLE will be cleared when the operation is complete.

Note:
  1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE synchronization is complete.
  2. This bit is not enable-protected.
ValueDescription
0 The EIC is disabled.
1 The EIC is enabled.

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded.

Note:
  1. When the CTRLA.SWRST is written, the user must poll SYNCBUSY.SWRST bit to know when the reset operation is complete.
  2. During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.
  3. This bit is not enable protected.
ValueDescription
0 There is no ongoing reset operation.
1 The reset operation is ongoing.